High scanning frequency COMS-TDI image sensor

ABSTRACT

The present invention relates to technical field of analog integrated circuit design. TDI function is better realized by CMOS image sensor and it improves scanning frequency of the CMOS-TDI image sensor and extends application range of TDI technique. To this end, the present invention proposes a technical solution of high scanning frequency CMOS-TDI image sensor. The pixels include a photodiode, an operational amplifier, integration capacitors C 1  and C 2  of the same capacitance, an offset voltage removing capacitor C 3 , and plural switches S 1 -S 10 . The anode of the photodiode is connected to a zero voltage ground wire, while the cathode thereof is connected to one end of the switch S 9 . The other end of the switch S 9  is connected to a reference voltage V ref . The above pixels are cascaded and an output end of the last pixel is connected to a column-parallel ADC through a readout switch Read. The invention mainly applies to analog integration circuit design.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from CN Application No. CN201410470253.5, filed Sep. 15, 2014 and PCT Application No. PCT/CN2014/093752, filed Dec. 12, 2014, the contents of which are incorporated herein in the entirety by reference.

TECHNICAL FIELD

The present invention relates to technical field of analog integrated circuit design and more particularly, relates to design of a COMS-TDI image sensor capable of realizing higher scanning frequency, that is, a high scanning frequency COMS-TDI image sensor.

BACKGROUND ART

An image sensor is able to transform optical signals acquired by a lens to electrical signals which are easy to be stored, transferred, and processed. In terms of operation manner, image sensors may be classified into area type and linear type. The working principle of area image sensor is as follows: photos of an object are taken according to pixel matrix of two dimensional area so as to obtain two dimensional image information, whereas the working principle of a linear image sensor is: photos of the object are taken according to pixel matrix of one dimension and by scanning the object to get the two dimensional image information. The working manner of a linear image sensor is demonstrated in FIG. 1. The linear image sensor works in a special manner and therefore it is widely applied in kinds of fields such as aerial photography, space imaging, machine vision, medical imaging, and so on. However, as the object keeps moving during pixel exposure of the linear image sensor, exposure period of pixels is seriously limited by moving speed of the linear image sensor corresponding to the object to which pictures are taken. In particular, in case of high movement and low illumination environment (for example in space imaging), the SNR (signal to Noise Ratio) of the linear image sensor will become very low. To resolve the problem of low SNR, time delay integration (TDI) has been proposed. It is able to increase SNR and sensitivity of the linear image sensor and it uses special scanning manner to expose the same object several times, thus realizing higher SNR and sensitivity. As such, it is suitable for environment of high movement and low illumination. The basic principles of TDI lie in linear scanning with area pixel matrix, thus realizing multiple exposure of the same moving object by pixels of different lines, and accumulating of exposure result of each time. This equivalently extends exposure integration time of the object, thereby greatly improving SNR and sensitivity.

In early period, TDI technique is implemented by using charge coupled device (CCD) image sensor which is also an ideal device for implementing TDI technique. It can realize accumulation of signals without noise. Currently, TDI technique mostly applies to CCD image sensor. A widely used CCD-TDI image sensor has the structure similar to a rectangular area CCD image sensor and performs linear scanning. Shown as FIG. 2, the operation of a CCD-TDI image sensor is as follows: N-leveled CCD-TDI image sensor has n lines pixels; the charges collected during a first exposure period by pixels of the first line of a row are not output directly, they are added to charges collected during a second exposure period by a second pixel located at the same row. By the same token, charges collected by the pixels of the last line (the n^(th) line) of the CCD-TDI image sensor are added into charges collected during the n-1^(th) and are read out according to the output manner of a normal linear CCD device. For a CCD-TDI image sensor, the amplitude of output signals is accumulation of integration charges of n pixels. It is equivalent to charges of a pixel collected during n times of exposure time. The output signal amplitude is increased by n times while the noise amplitude is increased only by √{square root over (n)} times and accordingly, SNR may be improved by √{square root over (n)} times.

However, as CCD image sensor has the disadvantages such as large power consumption and low integration, applications in various fields of CCD image sensor has been gradually replaced by CMOS (Complementary Metal Oxide Semiconductor) image sensor. If TDI function is able to be realized by CMOS image sensor (i.e., CMOS-TDI image sensor), cost of TDI camera will be decreased dramatically and find its wide application. In prior art, to realize TDI function using CMOS image sensor, analog signal accumulators are incorporated into the CMOS image sensor to work as a CMOS-TDI image sensor. That is, analog signals output by the pixels are in advance input into the analog signal accumulator to realize accumulation of the identically exposed signals, and the accumulated analog signals are sent to the ADC to be output quantitatively. Furthermore, prior art has also proposed to quantitatively output signals of the CMOS image sensor through the ADC at first and then, finish accumulation of identically exposed signals by a digital domain accumulator built in chip. These two kinds of techniques, either performing accumulation and then quantitative output or performing quantification and then accumulative output, are require reading out of exposure result of all pixels of the CMOS image sensor during a single exposure period. As a result, readout speed certainly will limit the shortest exposure period, i.e., the largest scanning frequency. To eliminate this problem, prior art has proposed integration of buffer cell into the pixels to realize signal delivery between adjacent pixels. Similar to CCD type TDI image sensor capable of realizing accumulation of signals in a pipelined manner, only the output of the last line of pixels during each exposure time needs to be read out quantitatively. Accordingly, limitation of the scanning frequency caused by readout speed is eliminated, thereby realizing faster scanning frequency. This technique, however, during pipelined accumulation of pixel output signal, will introduce a great deal of KT/C noise and offset voltage of the operational amplifier. In addition, fill factor of pixels is decreased due to integration of buffer cells into the pixels, hence limiting sensitivity of the sensor.

SUMMARY OF THE INVENTION

The present invention is intended to overcome drawbacks of prior art and to better realize TDI function of CMOS image sensor, improve scanning frequency of the CMOS-TDI image sensor, and extend application range of the TDI technique. To these ends, the present invention proposes a technical solution of high scanning frequency CMOS-TDI image sensor. It includes a photodiode, an operational amplifier, integration capacitors C1 and C2 of the same capacitance, an offset voltage removing capacitor C3, and plural switches S1-S10. The anode of the photodiode is connected to a zero voltage ground wire, while the cathode thereof is connected to one end of the switch S9. The other end of the switch S9 is connected to a reference voltage V_(ref). A left electrode plate of the offset voltage removing capacitor C3 is coupled to the cathode of the photodiode, whereas a right electrode thereof is coupled to a negative input end of the operational amplifier. The switch S1 0 is connected between the negative input end and an output end of the operational amplifier in series. A positive input end of the operational amplifier is coupled to the reference voltage V_(ref.) The output end of the operational amplifier also works as the output end of entire pixels. The left electrode plate of the integration capacitor C1 is connected to one end of each switch S1 and S3. The other end of the switch S1 is connected to the reference voltage V_(ref), the other end of the switch S3 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C1 is connected to one end of each switch S2 and S4. The other end of the switch S2 is connected to an input end of the pixel, and the other end of the switch S4 is connected to an output end of the pixel. The left electrode plate of the integration capacitor C2 is connected to one end of each switch S5 and S7. The other end of the switch S5 is connected to the reference voltage V_(ref), and the other end of the switch S7 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C2 is connected to one end of each switch S6 and S8. The other end of the switch S6 is connected to an input end of the pixel, and the other end of the switch S8 is connected to an output end of the pixel. The cascading manner of above pixels is described as follows: an input end of pixel 1 is connected to the reference voltage V_(ref), an input end of pixel 2 is connected to an output end of pixel 1 and then cascading by the similar manner; an output end of the last pixel is connected to a column-parallel ADC through a readout switch Read.

The switches S1 and S2 are controlled by the clock clk1′, the switches S3 and S4 are controlled by the clock clk2, the switches S5 and S6 are controlled by the clock clk2′, the switches S7 and S8 are controlled by the clock clk1, while the switches S9 and S10 are controlled by the clock rst. When the clock Read is at high level, the pixel output is valid. The following operation of pixels is done in a pipelined manner: sample the input signal, and then add the sampled signal to photocurrent integration signal generated during an exposure period of the pixel, output the accumulation result and express the output V_(int) as:

$\begin{matrix} {V_{int} = {V_{ref} + V_{0} + \frac{\int_{0}^{T_{iot}}{i_{ph}{dt}}}{C\; 1}}} & (1) \end{matrix}$

Wherein V₀ is signal collected during the previous exposure period of the pixel, and i_(ph) is photocurrent value of the photodiode.

The operating procedure of the pixel is described as follows:

In the initializing status, clk1=clk2=0, clk1′=clk2′=rst=1, the input and output voltage of all pixels are V_(ref) by this time. After that, all the pixels are subject to a first exposure period, and here, clk1=clk1′=1, clk2=clk2′=rst=0, the integration capacitor C1 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C2 begins to integrate photocurrent of the photodiode. When the first exposure period ends, the signal stored in the integration capacitor C2 of x^(th) pixel is V_(int(1,x)), and the signal stored in the integration capacitor C1 thereof is V_(int(1,x-1)). And then, all the pixels are subject to a resetting status and here, clk1=clk1′=clk2=clk2′=0, rst=1, and the integration capacitors C1 and C2 of each pixel are in a floating status by this time and signals stored in these capacitors are kept unchanged. Resetting action is done to the photodiode. After that, all the pixels are subject to a second exposure period and here, clk1=clk1′=rst=0, clk2=clk2′=1, the integration capacitor C2 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C1 begins to integrate photocurrent of the photodiode. When the second exposure period ends, the signal stored in the integration capacitor C1 of x^(th) pixel is V_(int(1,x-1))+V_(int(2,x)), and the signal stored in the integration capacitor C2 thereof is V_(int(1,x-2))+V_(int(2,x-1)). By the similar manner, after exposure of N times, the output of the N^(th) pixel can be expressed as:

V_(int) _(_) _(tot)=V_(int(1,1))+V_(int(2,2))+V_(int(3,3))+. . . +V_(int(N,N))   (2)

Wherein, from V_(int(1,1))to V_(int(N,N)), each represents exposure result of the same object during a respective transit time from 1 to N by a respective pixel from 1 to N. Accordingly, the output of the N^(th) pixel is the result of N-leveled integration accumulation. This result is quantitatively output by a subsequent column-parallel ADC during high level period of the clock Read, thus completing the entire reading out process. During each exposure period, the output of the N^(th) pixel is the result of N times integration accumulation.

The layout is denoted below.

A square with a central distance P is a photosensitive region of the photodiode, and a laterally adjacent square with the same size is the location where the operational amplifier, switches and capacitor layout are disposed and it is called as circuitry region. Every two laterally adjacent square constitute a layout of a pixel. Pixels of odd column are not laterally adjacent to those of even column. The pixels of even column entirely locate below the pixels of odd column. The photosensitive region of pixels of even column is aligned with the circuitry region of the pixels of odd column. Except for the first column, photosensitive region of pixels of odd column is aligned with the circuitry region of the pixels of even column. Consequently, along a direction perpendicular to the scanning direction, that is, the length direction of the sensor array, a photosensitive region of which the fill factor is almost 100% is disposed every distance of P.

The present invention has the following features and good effects.

The pixel structure of the CMOS-TDI image sensor is able to realize transfer the output signal of previous pixels to next pixels at exposure time, and obtained the pipelined accumulation of exposure result to the same object by the pixels of the same column. In each exposure period, output of the last line pixels is required to be read out, thus decreasing limitation of the shortest exposure time caused by readout speed, and improving the largest scanning frequency of the sensor. Offset isolation technique is employed to the pixels to remove offset voltage. In addition, only one sampling operation is introduced in the course of receiving forwarded pixel output signal, thus reducing the introduced thermal noise. The layout suitable for this pixel structure may significantly improve fill factor of the pixel photosensitive region without decreasing equivalent central distance of the pixels. The instant invention may better realize TDI function, improve scanning frequency of the CMOS-TDI image sensor, and expand application range of the TDI technique.

DESCRIPTION OF DRAWINGS

FIG. 1 shows a schematic operation manner of a prior art linear image sensor;

FIG. 2 shows schematic operation manner of a prior art CCD-TDI image sensor;

FIG. 3 shows a pixel circuit diagram employed by a high scanning frequency COMS-TDI image sensor of the present invention;

FIG. 4 indicates schematic pixel timing sequence control of the present invention;

FIG. 5 shows a circuit diagram of pixels of a single column of the present invention;

FIG. 6 shows a schematic layout view of the pixel array of the invention; and

FIG. 7 shows an embodiment schematic view of a single pixel layout of the current invention.

DETAILED DESCRIPTION OF THE INVENTION

The pixel structure employed by a COMS-TDI image sensor of the present invention is illustrated in FIG. 3. It mainly includes a photodiode, an operational amplifier, integration capacitors C1 and C2 (of the same capacitance value), an offset voltage removing capacitor C3, and plural switches S1-S10. These components of the pixel have the connection relationship as denoted below. The anode of the photodiode is connected to a ground wire (0V), while the cathode thereof is connected to one end of the switch S9, the other end of the switch S9 is connected to a reference voltage V_(ref). A left electrode plate of the offset voltage removing capacitor C3 is coupled to the cathode of the photodiode, whereas a right electrode thereof is coupled to a negative input end of the operational amplifier. The switch S10 is connected between the negative input end and an output end of the operational amplifier in series. A positive input end of the operational amplifier is coupled to the reference voltage V_(ref). The output end of the operational amplifier also works as the output end of entire pixels. The left electrode plate of the integration capacitor C1 is connected to one end of each switch S1 and S3, the other end of switch S1 is connected to the reference voltage V_(ref), and the other end of the switch S3 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C1 is connected to one end of each switch S2 and S4. The other end of the switch S2 is connected to an input end of the pixel, the other end of the switch S4 is connected to an output end of the pixel. The left electrode plate of the integration capacitor C2 is connected to one end of each switch S5 and S7. The other end of the switch S5 is connected to the reference voltage V_(ref), the other end of the switch S7 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C2 is connected to one end of each switch S6 and S8. The other end of the switch S6 is connected to an input end of the pixel, the other end of the switch S8 is connected to an output end of the pixel. The controlling timing sequence of the switches S1-S10 is shown in FIG. 4. Wherein, T_(L) is transit time, T_(int) is pixel exposure time, high level indicates turning on of the switches, while low level indicates turning off thereof. Also, the switches S1 and S2 are controlled by the clock clk1′, the switches S3 and S4 are controlled by the clock clk2, the switches S5 and S6 are controlled by the clock clk2 ′, the switches S7 and S8 are controlled by the clock clk1, while the switches S9 and S10 are controlled by the clock rst. When the clock Read is at high level, the pixel output is valid. Under control of timing sequence of FIG. 4, the pixel structure of FIG. 3 may perform the following actions in a pipelined manner: sample the input signal, and then add the sampled signal to photocurrent integration signal generated during an exposure period of the pixel, output the accumulation result and express the output V_(int) as:

$\begin{matrix} {V_{int} = {V_{ref} + V_{0} + \frac{\int_{0}^{T_{iot}}{i_{ph}{dt}}}{C\; 1}}} & \left( {{formula}\mspace{14mu} 1} \right) \end{matrix}$

Wherein V₀ is signal collected during the previous exposure period of the pixel, and i_(ph) is photocurrent value of the photodiode. The offset voltage removing capacitor C3 of the pixel has the ability of isolating integration capacitors C1 and C2 from the operational amplifier offset voltage. As a result, integration result output by the pixel contains no offset voltage of the operational amplifier. Moreover, only one input signal sampling operation is introduced in the course of signal accumulation by the pixel. That is, sampling thermal noise is introduced only for one time, thus reducing thermal noise level during accumulated readout.

TDI signal accumulation function is achieved by cascading these pixels. A single column of pixels after cascading N pixels is illustrated in FIG. 5. Here, an input end of pixel 1 is connected to the reference voltage V_(ref), an input end of pixel 2 is connected to an output end of pixel 1 and then cascading by the similar manner; and finally, an output end of the last pixel is connected to a column-parallel ADC through a readout switch Read. The operating procedure of the pixel is described as followed. In the initializing status, (clk1=clk2=0, clk1′=clk2′=rst=1), the input and output voltage of all pixels are V_(ref) by this time, resetting action is finished for integration capacitors C1 and C2 of all pixels, and resetting action is also done to the photodiode. After that, all the pixels are subject to a first exposure period(clk1=clk1′=1, clk2=clk2′=rst=0), the integration capacitor C1 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C2 begins to integrate photocurrent of the photodiode. When the first exposure period ends, the signal stored in the integration capacitor C2 of x^(th) pixel is V_(int(1,x)), and the signal stored in the integration capacitor C1 thereof is V_(int(1,x-1)). Next, all the pixels are subject to a resetting status (clk1=clk1′=clk2=clk2′=0, rst=1), the integration capacitors C1 and C2 of each pixel are in a floating status by this time and signals stored in these capacitors are kept unchanged. Resetting action is done to the photodiode. After that, all the pixels are subject to a second exposure period(clk1=clk1′=rst=0, clk2=clk2′=1), the integration capacitor C2 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C1 begins to integrate photocurrent of the photodiode. When the second exposure period ends, the signal stored in the integration capacitor C1 of x^(th) pixel is V_(int(1,x-1))+V_(int(2,x)), and the signal stored in the integration capacitor C2 thereof is V_(int(1,x-2))+V_(int(2,x-1)). By the similar manner, after exposure of N times, the output of the N^(th) pixel may be expressed as:

V_(int) _(_) _(tot)=V_(int(1,1))+V_(int(2,2))+V_(int(3,3))+. . . +V_(int(N,N))   (formula 2)

Wherein, from V_(int(1,1)) to V_(int(N,N)), each represents exposure result of the same object during a respective transit time from 1 to N by a respective pixel from 1 to N. Accordingly, the output of the N^(th) pixel is the result of N-leveled integration accumulation. This result is quantitatively output by a subsequent column-parallel ADC during high level period of the clock Read, thus completing the entire reading out process. During each exposure period, the output of the N^(th) pixel is the result of N times integration accumulation. Therefore, the ADC only needs to perform readout for one time, thus reducing limitation of the scanning frequency imposed by readout speed. A readout time of microsecond level can lead to a scanning frequency of hundreds of KHz.

Operational amplifiers and capacitors are integrated into the pixel structure of the invention, and these circuits certainly reduce fill factor of the photosensitive region of the photodiode. To overcome this problem, the present invention suggests a layout as shown in FIG. 6 and suitable for this pixel structure. Here, each square has a central distance of P. the hatched squares are photosensitive regions of the photodiode, while laterally adjacent white squares with the same size are locations where the operational amplifier and capacitor layout are disposed (are called as circuitry regions). Accordingly, each hatched square and a laterally adjacent white square constitute a layout of a pixel. Pixels of odd column are not laterally adjacent to those of even column. The pixels of even column entirely locate below the pixels of odd column. The photosensitive region of pixels of even column is aligned with the circuitry region of the pixels of odd column. Except for the first column, photosensitive region of pixels of odd column is aligned with the circuitry region of the pixels of even column. Consequently, along a direction perpendicular to the scanning direction (that is, the length direction of the sensor array), a photosensitive region of which the fill factor is almost 100% is disposed every distance of P. By using such layout, influence of the circuit portion of the pixel on the fill factor of the photosensitive regions is decreased without decreasing equivalent pixel central distance, and almost 100% of fill factor can be formed. Only a constant time difference N×TL exists between output of odd and even columns of pixels. This difference may be removed by simply handling output digital signals and this will not burden post circuits.

To make clear objects, technical solution and advantages of the invention, detailed description will be provided to the embodiments of the invention in connection with examples. In this embodiment, the length of the sensor is 1024 pixels, levels of the TDI are 50, scanning frequency is 100 KHz, the central distance of pixel photosensitive region is 15 μm, and a Cyclic ADC with a resolution of 10 bit and conversion rate of 100 KHz is used as a column-parallel on-chip ADC. The layout of an individual pixel is shown in FIG. 7. The photodiode has the size of 15 μm×15 μm, capacitors C1, C2 and C3, switches and operational amplifier are all placed into a 15 μm×15 μm sized layout. Here, the size of the capacitors C1, C2 is both 7.5 μm×7.5 μm, the capacitor C3 has the size of 2.5 μm×15 μm, the rest area is for placing the switches and operational amplifier. If the capacitors are realized by a MIM capacitor with a unit area capacitance of 2 fF/μm², then the capacitance value of the capacitors C1, C2 will be about 112.5 fF, while that of the capacitor C3 will be about 75 fF. Moreover, MIM is generally made of upper layer of metal and as a result, transistors and lower layer of metal wiring may be positioned below the capacitors. As such, part of switches and operational amplifiers may be disposed into the space below the capacitors to make full use of space. The length of the sensor pixel array is 15 μm×1024=15360 μm, height is 15 μm×50×2=1500 μm, and equivalent photosensitive region central distance is 15 μm. Regarding scanning frequency of 100 KHz, the transit time T_(L) of the sensor is 10 μs, including 9 μs of T_(int) and 1 μs of pixel resetting time. The conversion rate of in-chip column-parallel ADC is 100 KHz which meeting the requirement of readout speed. During period of sampling previous pixel output by each pixel, the root mean square value of introduced thermal noise is √{square root over (kT/C₁)}≈192 μV. Accordingly, after accumulation of TDI of 50 levels, the root mean square value of introduced total thermal noise is √{square root over (50kT/C₁)}≈1.36 mV. The reference voltage V_(ref) of the pixel may be 1V. If the maximum voltage output by the pixel is 2.6V, the maximum signal amplitude output by the pixels after accumulation of 50 levels is 1.6V. If only thermal noise caused during readout process is considered, the maximum SNR of the output signals is 20 log (1.6V/1.36 mV)=61.4 dB, satisfying SNR requirement of ADC of 10-bit resolution. 

What is claimed is:
 1. A high scanning frequency CMOS-TDI image sensor, wherein a pixel comprises a photodiode, an operational amplifier, integration capacitors C1 and C2 of the same capacitance, an offset voltage removing capacitor C3, and plural switches S1-S10; the anode of the photodiode is connected to a zero voltage ground wire, while the cathode thereof is connected to one end of the switch S9; the other end of the switch S9 is connected to a reference voltage V_(ref); a left electrode plate of the offset voltage removing capacitor C3 is coupled to the cathode of the photodiode, whereas a right electrode thereof is coupled to a negative input end of the operational amplifier;the switch S10 is connected between the negative input end and an output end of the operational amplifier in series; a positive input end of the operational amplifier is coupled to the reference voltage V_(ref); the output end of the operational amplifier also works as the output end of entire pixels; the left electrode plate of the integration capacitor C1 is connected to one end of each switch S1 and S3; the other end of the switch S1 is connected to the reference voltage V_(ref); the other end of the switch S3 is connected to the cathode of the photodiode; the right electrode plate of the integration capacitor C1 is connected to one end of each switch S2 and S4; the other end of the switch S2 is connected to an input end of the pixel; the other end of the switch S4 is connected to an output end of the pixel; the left electrode plate of the integration capacitor C2 is connected to one end of each switch S5 and S7; the other end of the switch S5 is connected to the reference voltage V_(ref); the other end of the switch S7 is connected to the cathode of the photodiode; the right electrode plate of the integration capacitor C2 is connected to one end of each switch S6 and S8; the other end of the switch S6 is connected to an input end of the pixel; the other end of the switch S8 is connected to an output end of the pixel; the cascading manner of above pixels is described as follows: an input end of pixel 1 is connected to the reference voltage V_(ref), an input end of pixel 2 is connected to an output end of pixel 1 and then cascading by the similar manner; an output end of the last pixel is connected to a column-parallel ADC through a readout switch Read.
 2. The high scanning frequency CMOS-TDI image sensor according to claim 1, wherein the switches S1 and S2 are controlled by the clock clk1′, the switches S3 and S4 are controlled by the clock clk2, the switches S5 and S6 are controlled by the clock clk2′, the switches S7 and S8 are controlled by the clock clk1, while the switches S9 and S10 are controlled by the clock rst; when the clock Read is at high level, the pixel output is valid; the following operation of pixels is done in a pipelined manner: sample the input signal, and then add the sampled signal to photocurrent integration signal generated during an exposure period of the pixel, output the accumulation result and express the output V_(int) as: $\begin{matrix} {V_{int} = {V_{ref} + V_{0} + \frac{\int_{0}^{T_{iot}}{i_{ph}{dt}}}{C\; 1}}} & (1) \end{matrix}$ wherein V₀ is signal collected during the previous exposure period of the pixel, and i_(ph) is photocurrent value of the photodiode.
 3. The high scanning frequency CMOS-TDI image sensor according to claim 1, wherein the operating procedure of the pixel is described as followed: in the initializing status, clk1=clk2=0, clk1′=clk2′=rst=1; the input and output voltage of all pixels are _(Vref) by this time; after that, all the pixels are subject to a first exposure period, and here, clk1=clk1′=1, clk2=clk2′=rst=0; the integration capacitor C1 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C2 begins to integrate photocurrent of the photodiode; when the first exposure period ends, the signal stored in the integration capacitor C2 of x^(th) pixel is V_(int(1,x)), and the signal stored in the integration capacitor C1 thereof is V_(int(1,x-1)); next, all the pixels are subject to a resetting status and here, clk1=clk1′=clk2=clk2′=0, rst=1; the integration capacitors C1 and C2 of each pixel are in a floating status by this time and signals stored in these capacitors are kept unchanged; resetting action is done to the photodiode; after that, all the pixels are subject to a second exposure period and here, clk1=clk1′=rst=0, clk2=clk2′=1;the integration capacitor C2 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C1 begins to integrate photocurrent of the photodiode; when the second exposure period ends, the signal stored in the integration capacitor C1 of x^(th) pixel is V_(int(1,x-1))+V_(int(2,x)), and the signal stored in the integration capacitor C2 thereof is V_(int(1,x-2))+V_(int(2,x-1)); by the similar manner, after exposure of N times, the output of the N^(th) pixel may be expressed as: V_(int) _(_) _(tot)=V_(int(1,1))+V_(int(2,2))+V_(int(3,3))+. . . +V_(int(N,N))   (2) Wherein, from V_(int(1,1)) to V_(int(N,N)), each represents exposure result of the same object during a respective transit time from 1 to N by a respective pixel from 1 to N; accordingly, the output of the N^(th) pixel is the result of N-leveled integration accumulation; this result is quantitatively output by a subsequent column-parallel ADC during high level period of the clock Read, thus completing the entire reading out process; during each exposure period, the output of the N^(th) pixel is the result of N times integration accumulation.
 4. The high scanning frequency CMOS-TDI image sensor according to claim 1, wherein the layout is denoted below: a square with a central distance P is a photosensitive region of the photodiode, and a laterally adjacent square with the same size is the location where the operational amplifier, switches and capacitor layout are disposed and it is called circuitry region; every two laterally adjacent square constitute a layout of a pixel; pixels of odd column are not laterally adjacent to those of even column; the pixels of even column entirely locate below the pixels of odd column; the photosensitive region of pixels of even column is aligned with the circuitry region of the pixels of odd column; except for the first column, photosensitive region of pixels of odd column is aligned with the circuitry region of the pixels of even column; consequently, along a direction perpendicular to the scanning direction, that is, the length direction of the sensor array, a photosensitive region of which the fill factor is almost 100% is disposed every distance of P. 